What is makefile? Most Windows developers don’t know this, and it is useful in Linux development. Most often, the makefile directs Make on how to compile and link a program.
Make sure you have installed gcc before learning.
Try the following command:
It means, preprocess only with
hello.c; do not compile, assemble or link. Then output to
You can read the output file
hello.i and try to understand this file.
Compile is the most important step, it transform the preprocessing file into an assembly file.
It means, compile only
hello.i; do not assemble or link. Then output to
hello.s, which is an assembly file.
After compiling, you need to assemble it to an object file.
It means, compile and assemble
hello.s, but do not link. Then output to
hello.o, which is an object file.
The final step is link.
Now you can run this program by the following command:
You can run the following command without the generation of intermediate file, but the actual process will not change.
= is the most basic assignment;
:= is the value before the override;
?= is the value after the sign if it has not been assigned;
+= is the value after adding the sign.
targetcould be an object file, executable file or just a target.
prerequisite) are the file used in the make process. If nothing used, keep empty.
system command(s)(also called
recipe) is an action that make carries out, usually use shell command.
And the example could be also described as follow:
The order of makefile does not affect the execution results, but for the readability, it is best to use the top-down order.
There are many advantages to use phony target. One is to avoid the name conflict between the command only target defined in the makefile and the actual file in the working directory; the other is the efficiency of submitting and executing the makefile.
.PHONY to define the phony target, such as following:
.PHONY can define more than one target:
If you have two targets or more to build, you may try to write as follows:
This cannot help you compile two targets or more, if you check the built files, you won’t see
main_b. The reason is that makefile only processes the top one, and
main_a doesn’t rely on
main_b won’t be built.
The solution is use
all:, like follows:
all become the top one, and it rely on
main_b, so all targets will be built.
If the compiler now instead of
gcc, we use
clang++, and we don’t want to change every
gcc because it is too trouble. We can use abstract build to solve the problem.
We can define a variable
CC = gcc, and use it by using
Then, we can use more and more variable to abstract this file.
Use the pattern rules can help you batch build:
$@: Target files.
$^: Dependencies files.
$<: First dependency file.
$%: When the target file is a static library file, it represents a member name of the static library.
$?: A list of all dependent files that are newer than the target file, separated by spaces. If the target file is a static library file, it represents a library file(
If the source code in the folder but not the current directory, you may use
It means the source code in the
If you want to define more than one
VPATH, use follows:
Selective search files from a directory.
Clean the vpath for %.c:
Clean the vpath for all:
Include other makefile:
When the included file doesn’t exist or there are no rules to create it, if you want make will continue to execute the program (Only when the ultimate goal reconstruction can’t be completed, our program will prompt error save and exit.), you can use follows: